NXP Semiconductors MPC5644A, Reference Manual, Page: 838 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
838 Freescale Semiconductor
parameter access of a thread is atomic in relation to another thread in the same engine, since a thread
cannot be suspended (pre-empted).
For 1 parameter coherent access, or dual-parameter coherency between only one Microengine and Host,
the alternatives shown in previous sections apply.
24.5.4.3 Coherent Dual-parameter Controller (CDC)
Dual-parameter coherency is supported by a Coherent Dual-parameter Controller hardware (CDC), which
contends with microengine for SPRAM access. CDC atomically transfers, upon Host’s command, two
parameters from one area of the SPRAM to another. One area is a temporary (buffer) area, where the two
parameters are directly read or written by the Host. This temporary area has to begin in an SPRAM address
multiple of 2 words, and the two parameters must be sequential. The other area is the channel parameter
area where the microcode normally accesses the parameters, usually with the channel relative address
mode (see
Section 24.5.9.1.1, SPRAM Addressing Modes ). In this area, the parameters transferred by
CDC don’t have to be sequential. A transfer from the temporary area to the channel area, when the Host
sends data to the channel, is called a
write transfer . Inversely, in a read transfer the parameters are copied
from the channel area to the temporary area (channel to Host).
Coherency is guaranteed by the SPRAM access contention rules implemented in the SPRAM arbiter (see
Section 24.5.4.5, SPRAM Arbitration ). CDC transfers are coherent in respect to the two engines, so the
target parameters in the channel area may be shared by channels on them both. During CDC operation, the
Host may suffer from 3 up to 11 system clocks wait states
1
, and the Microengine(s) may suffer up to 2
microcycle wait-states
2
. CDC accesses are atomic with respect to Microengine(s) accesses to the SPRAM.
Even when neither engine is in TST, CDC may suffer up to 4 system clock internal wait-states from
SPRAM arbiter, meaning 9 slave wait-states to Host, so that it does not break atomic back-to-back accesses
from microengine(s). CDC also cannot break TST preload accesses. Host can initiate CDC back-to-back
transfers: there is no need of idle slave cycles between two transfers.
24.5.4.3.1 CDC Programming
The Coherent Dual-parameter Controller Register (see Section 24.4.2.2, ETPU_CDCR – eTPU Coherent
Dual-Parameter Controller Register ) is used to configure and initiate CDC transfers between the
temporary area and channel parameter area. Host asserts STS bit in order to start the data transfer. CDC
then contends for the SPRAM and starts the transfer. When the data transfer is complete, STS returns to 0.
Host receives wait-states for writing STS = 1 while CDC contends for SPRAM and during the transfer.
The write access ends when CDC finishes the transfer. Host receives wait-states during the CDC transfer.
If Host writes ETPU_CDCR with STS = 0 or does not write the STS byte, the CDC transfer does not occur.
CDC programming can be summarized as follows:
1. If it is a write transfer, i.e., from Host to channel, write the two parameters into temporary area.
1. The maximum number of Host wait states on CDC occurs when both microengines overlap their TSTs, delayed 3 system
clocks from each other.
2. One microcycle takes two system clocks. Microengines get wait-states in multiples of microcycles, while Host and CDC
wait-states are multiples of system clocks.