Reaction Module (REACM)
MPC5644A Microcontroller Reference Manual, Rev. 6
700
Freescale Semiconductor
23.3.4
REACM Threshold Router Register (REACM_THRR)
The REACM Threshold Router Register (REACM_THRR) routes the ADC result to the Threshold Bank.
Since a TAG is assigned for each ADC result coming from the on-chip ADC module, this TAG is specified
in this register and used for the routing process. These ADC result is written to the Threshold Value Bank
as soon as it is received by the Reaction Module. Note that THRADC0 and THRADC1 TAG values may
also be used by the reaction channels. In this case the results are routed to both, the channel and the
Threshold Bank.
NOTE
Due to the timing in which these parallel events occur, if the channel uses
the same Threshold Bank address in which the incoming ADC result was
written to, this ADC result is used for the channel modulation being
executed.
Figure 23-6. REACM Threshold Router Register (REACM_THRR)
Table 23-5. REACM_TCR field descriptions
Field
Description
0–3
Reserved, should be cleared.
4–15
HPRE
[11:0]
Hold-off Timer Prescaler
The HPRE[11:0] field defines the rate of the Hold-off Timers on each reaction channel. If its value is zero
the prescaler is bypassed thus the Hold-off timer operates at the module clock rate. If HPRE = 0x01 the
module operates at module clock divide by two and so forth up to HPRE = 0xFFF which defines system
clock divided by 4096.
16–23
Reserved, should be cleared.
24–31
TPRE
[7:0]
Timer Prescaler
The TPRE[7:0] field defines the rate of the Timers on the Timer bank. If its value is zero the prescaler is
bypassed thus the Timer operates at the module clock rate. If TPRE = 0x01 the Timer operates at
module clock divide by two and so forth up to TPRE = 0xFF which defines module clock divided by 256
as the frequency of operation for the Timer.
Address: REACM_BASE (0xC3FC_7000) + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
WREN1
WREN0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
THRADC1[3:0]
0
0
0
0
THRADC0[3:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Summary of Contents for MPC5644A
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