NXP Semiconductors MPC5644A, Reference Manual, Page: 1449 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1449
0x0012 PE DRAM Data Register (FR_PEDRDR) R/W on page
33-1463
Interrupt and Error Handling
0x0014 Protocol Operation Control Register (FR_POCR) R/W on page
33-1464
0x0016 Global Interrupt Flag and Enable Register (FR_GIFER) R/W on page
33-1465
0x0018 Protocol Interrupt Flag Register 0 (FR_PIFR0) R/W on page
33-1468
0x001A Protocol Interrupt Flag Register 1 (FR_PIFR1) R/W on page
33-1470
0x001C Protocol Interrupt Enable Register 0 (FR_PIER0) R/W on page
33-1471
0x001E Protocol Interrupt Enable Register 1 (FR_PIER1) R/W on page
33-1473
0x0020 CHI Error Flag Register (FR_CHIERFR) R/W on page
33-1474
0x0022 Message Buffer Interrupt Vector Register (FR_MBIVEC) R on page
33-1476
0x0024 Channel A Status Error Counter Register (FR_CASERCR) R on page
33-1477
0x0026 Channel B Status Error Counter Register (FR_CBSERCR) R on page
33-1477
Protocol Status
0x0028 Protocol Status Register 0 (FR_PSR0) R on page
33-1478
0x002A Protocol Status Register 1 (FR_PSR1) R on page
33-1479
0x002C Protocol Status Register 2 (FR_PSR2) R on page
33-1480
0x002E Protocol Status Register 3 (FR_PSR3) R/W on page
33-1482
0x0030 Macrotick Counter Register (FR_MTCTR) R on page
33-1484
0x0032 Cycle Counter Register (FR_CYCTR) R on page
33-1484
0x0034 Slot Counter Channel A Register (FR_SLTCTAR) R on page
33-1485
0x0036 Slot Counter Channel B Register (FR_SLTCTBR) R on page
33-1485
Table 33-3. FlexRay memory map (continued)
Offset Register Access Location