NXP Semiconductors MPC5644A, Reference Manual, Page: 563 / 1735

Frequency-modulated phase locked loop (FMPLL)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 563
17.3.1 Detailed signal descriptions
Table 17-4 describes the external signals used by the FMPLL.
17.4 Memory map and register definition
This section provides the memory map and detailed descriptions of all registers of the FMPLL.
17.4.1 Memory map
Table 17-5 shows the memory map. Addresses are given as offsets of the module base address.
Table 17-3. Signal properties
Name Function I/O Pull
PLLREF Configures the FMPLL clock reference at reset I/O Up
XTAL Output drive for external crystal O —
EXTAL_EXTCLK Crystal/external clock input I/O —
VDDPLL Analog power supply (1.2V +/

10%) Power —
VSSPLL
1
1
This signal is internally bonded to VSS.
Analog ground Groun
d
—
Table 17-4. FMPLL detailed signal descriptions
Signal
I/
O
Description
PLLREF I/
O
PLL reference—Determines the reset state of the CLKCFG[2] bit in FMPLL_ESYNCR1.
The PLLREF pin must be kept stable during system reset. After reset, this pin has no effect
on the PLL configuration, therefore it can be assigned to another function such as GPIO.
State
meaning Asserted—Indicates that the reference clock comes from the crystal oscillator.
Negated—Indicates that the reference clock comes from the external clock
generator.
Timing Assertion or negation—Must be done at the beginning of the reset cycle and
then kept stable for the whole reset duration.
XTAL O Crystal oscillator—Output for an external crystal oscillator.
EXTAL_EXTCLK I/
O
Crystal oscillator/external clock input—This pin is the input for an external crystal oscillator
or an external clock source. The function of this pin is determined by the CLKCFG[2] bit in
FMPLL_ESYNCR1, whose reset value is determined by the PLLREF pin.
VDDPLL / VSSPLL — PLL power supply—These are the 1.2V supply and ground for the FMPLL.