NXP Semiconductors MPC5644A, Reference Manual, Page: 1293 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1293
Field DSPI_SR[TXNXTPTR] indicates which TX FIFO Entry will be transmitted during the next transfer.
Field DSPI_SR[TXNXTPTR] contains the positive offset from DSPI_TXFR0 in number of 32-bit
registers. For example, TXNXTPTR equal to two means that the DSPI_TXFR2 contains the SPI data and
command for the next transfer. Field DSPI_SR[TXNXTPTR] is incremented every time SPI data is
transferred from the TX FIFO to the shift register. The maximum value of the field is equal to
DSPI_HCR[TXFR] and it rolls over after reaching the maximum.
30.9.2.4.1 Filling the TX FIFO
Host software or other intelligent blocks can add (push) entries to the TX FIFO by writing to the
DSPI_PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) in the DSPI_SR is set. The
TFFF bit is cleared when TX FIFO is full and the DMA controller indicates that a write to DSPI_PUSHR
is complete. Writing a ‘1’ to the TFFF bit also clears it. The TFFF can generate a DMA request or an
interrupt request. See
Section 30.9.10.2, Transmit FIFO fill interrupt or DMA request , for details.
The DSPI ignores attempts to push data to a full TX FIFO, the state of the TX FIFO does not change and
no error condition is indicated.
30.9.2.4.2 Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO Counter
decrements by one. At the end of a transfer, bit DSPI_SR[TCF] is set to indicate the completion of a
transfer. The TX FIFO is flushed by writing a ‘1’ to bit DSPI_MCR[CLR_TXF].
If an external bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is empty,
the Transmit FIFO Underflow Flag (TFUF) in the slave’s DSPI_SR is set. See
Section 30.9.10.4, Transmit
FIFO underflow interrupt request , for details.
30.9.2.5 Receive first-in first-out (RX FIFO) buffering mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds from 1 to 16
received SPI data frames. The number of entries in the RX FIFO is device specific. SPI data is added to
the RX FIFO at the completion of a transfer when the received data in the shift register is transferred into
the RX FIFO. SPI data are removed (popped) from the RX FIFO by reading the DSPI POP RX FIFO
Register (DSPI_POPR). RX FIFO entries can only be removed from the RX FIFO by reading the
DSPI_POPR or by flushing the RX FIFO.
The RX FIFO Counter field DSPI_SR[RXCTR] indicates the number of valid entries in the RX FIFO.
Field DSPI_SR[RXCTR] is updated every time the DSPI _POPR is read or SPI data is copied from the
shift register to the RX FIFO.
Field DSPI_SR[POPNXTPTR] points to the RX FIFO entry that is returned when the DSPI_POPR is read.
Field DSPI_SR[POPNXTPTR] contains the positive offset from DSPI_RXFR0 in number of 32-bit
registers. For example, POPNXTPTR equal to two means that the DSPI_RXFR2 contains the received SPI
data that will be returned when DSPI_POPR is read. Field DSPI_SR[POPNXTPTR] is incremented every