NXP Semiconductors MPC5644A, Reference Manual, Page: 938 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
938 Freescale Semiconductor
NOTE
Whenever BS = (constant) 0, its size is considered 8 bits, and all 24 bits in
B-bus are set to 0. Therefore, all operations with BS = (constant) 0 have
their size determined by AS and Destination only.
CCS field (1 bit) controls whether flags will be updated or not ( Table 24-85 ). When CCS bit exists in a
microinstruction, the operation size will be used to sample flags. In some microinstructions CCS field is
replaced by CCSV (2 bits,
Table 24-84 ). Flag sampling according to CCSV can be set as defined by the
operation size, or fixed as 8 or 16-bit operations.
NOTE
For the post-ALU rotate right operation, CCSV also determines the rotate
size: whether 8-bit, 16-bit, or determined by the operation size.
When neither CCS nor CCSV are present in the microinstruction, flags are not sampled. CCS and CCSV
do not affect the Carry update on Exchange Bit operation (see
Section 24.5.8.2.6, Exchange bit ), but does
control the N and Z flags.
24.5.9.2.4 B-Source inversion
The data selected as second source (T4BBS) can be inverted (bitwise boolean NOT) before operation. This
is controlled by microinstruction field BINV (1 bit,
Table 24-86 ). A zero value for BINV activates
B-source inversion.
24 bits x 24 bits 24 bits
x 24 bits 24 bits 24 bits
Table 24-84. Flag Sampling Using CCSV field
CCSV Meaning
00 sample flags as an 8 bit operation
01 sample flags as a 16 bit operation
10 sample flags as defined by operation size
11 do not sample flags
Table 24-85. Flag Sampling Using CCS field
CCS Meaning
0 sample flags as defined by operation size
1 do not sample flags
Table 24-83. Operation size determination
A Source B Source Destination Operation size