Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
855
To unburden the microengine, SRI asserted configures a channel “dumb” regarding the servicing of match
and capture channel service requests. Even with SRI = 1, TDLA/B and MRLA/B can still be asserted, and
the level specified by the OPAC (Output Pin Action Control) registers will be output to the pin.
Flag1,Flag0 – Channel “state resolution” flags
Each channel has a pair of flags, simply called Flag0 and Flag1, that can be set/reset by microcode through
microinstruction field FLC. FLC sets/resets Flag0/1 of the channel selected by CHAN. These flags can be
tested by microcode, and are also used to resolve the microcode entry point for the channel service (see
Section 24.5.1.1, Entry points
). Flag0 and Flag1 are, so, typically used for fast state resolution. FLC
microinstruction field also allows Flag1,Flag0 to be copied from selected bits of P register high byte,
which is also meant to be used to hold application state. Flag0 and Flag1 are both zero out of reset.
24.5.5.2
Match Recognition
The match operation is performed every microcycle by comparing the channel MatchA and MatchB
registers against the value of the TCR bus specified for each match. TCR1 or TCR2 bus is selected
according to TBSA and TBSB fields. Both results have effect on the next clock cycle (see
).
A Match A/B event is qualified by a set of match enabling conditions to the Match Recognition Registers
MRLA/B. To recognize the match and assert these registers, the following match enabling conditions are
required:
•
For IPACA/B = 0xx, Match Enable Flag (MEF), qualified by the channel currently being serviced
must be asserted. For IPACA/B = 1xx, Match A/B is always enabled (even during Time Slot
Transition (TST)), regardless of the state of the Match Enable Flag (MEF). See
for the conditions of MEF assertion.
•
Match Recognition Latch Enable 1/2 (MRLEA/B) is asserted. A match event recognition may only
occur if its corresponding MRLEA/B bit is set, which only happens upon a write to a channel match
register by the microcode, copied from ERTA/B. MRLEA/B is negated when the respective match
occurs or, in some double match channel modes, when a match for the other Match register occurs.
It ensures that the greater-equal comparison will not cause additional matches
1
.
•
In selected modes (see
Section 24.5.5.4, Channel Modes
), the particular conditions of MRL and
TDL flags of the other event, i.e:
— MRLA, TDLA enable or block MRLB;
— MRLB, TDLB enable or block MRLA.
•
The respective MRL is negated.
•
In selected modes (see
Section 24.5.5.4, Channel Modes
), the state of its respective TDL flag.
If the Match A and/or Match B conditions are met, the channel immediately forces the pin state if specified
by the appropriate OPACA/B registers (Output Pin Action Control 1/2) and, in some cases, by IPACA/B
registers. Refer to
Section , IPACA,IPACB and OPACA,OPACB – Input and Output Pin Action Control
1. Microcode can also negate MRLEA/B.
Summary of Contents for MPC5644A
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