NXP Semiconductors MPC5644A, Reference Manual, Page: 856 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
856 Freescale Semiconductor
If both Match A and Match B events occur at the same time, with conflicting pin actions, the priority over
the pin action is mode dependent. For further details on pin action resolution refer to
Section ,
Match/Transition Pin Action Conflict Resolution .
24.5.5.2.1 MRLA/B – Match Recognition Latches
MRLA/B indicate the recognition of a match event detected by the comparator. They can be asserted either
on T2 or T4 (see
Section 24.7.1, Microcycle and I/O timing ). Assertion of MRLA/B issues a match Service
Request in specific channel modes, depending on previous events and state of SRI. After reset MRLA and
MRLB are both negated.
When MRLA or MRLB is asserted, it may change the output signal level according to the Input and Output
Pin Action Control registers (refer to
Section , IPACA,IPACB and OPACA,OPACB – Input and Output
Pin Action Control Registers ). Assertion of MRLA/B causes a capture of one or two time bases, according
to the selected mode capturing scheme (see Section 24.5.5.3, Transition Detection and Time Base
Capture ).
A match recognition is self-blocking, regardless of Channel Mode: once MRLA (MRLB) has been
asserted, it negates its associated MRLEA (MRLEB) register, preventing future match recognitions, until
the associated match register is rewritten by microcode. The microcode has to enable new matches by
updating the new match value in the MatchA (MatchB) register
1
. In addition, assertion of MRLA/B can
block its twin MRLB/A, depending on the channel mode. In some double match blocking channel modes,
Match A/B event blocks the occurrence of Match B/A in a “first win” scheme.
It is the transition from 0 to 1 in MRL that causes the Match actions: apart from MRLEA/B negation(s),
no action due to a Match occurs if MRL was already set to 1, even if the other MRL assert conditions are
satisfied. However, if a Match and a microoperation negating its corresponding MRL occur at the same
time, MRL negation by microcode overrides its assertion, but any dependable captures and pin action
occurs anyway (if MRL was already negated before), and also the negation of MRLE(s) (the respective
one and, in some channel modes, the other, regardless of MRL state before). Note that MRLE must have
been set before (by writing a new Match value).
24.5.5.2.2 MEF – Match Enable Flag
MEF is a one-bit latch that is unique for all channels in an engine.
MEF can selectively enable assertion of MRLA/B, depending on the IPACA/B field. For IPACA/B = 0xx,
MEF = 1 enables assertion of MRLA/B for the scheduled channel during service. For IPACA/B = 1xx,
Match A/B is always enabled, regardless the state of the MEF, but it still depends on the other Match
recognition conditions. Matches of channels not being serviced are never disabled by MEF.
MEF is not accessible by Microengine or Host. MEF is negated for one microcycle in the middle of the
time slot transition period. After two microcycles (plus wait-states) into TST, the ME bit in the entry point
is copied to MEF to allow selective enabling of MRL for each thread (refer to
Section 24.5.1.2, Time slot
transition ). MEF is asserted unconditionally soon after a thread ends.
1. Before that, microcode should also negate MRLA (MRLB), otherwise an old match may be recognized by the scheduler and
serviced as a new one