NXP Semiconductors MPC5644A, Reference Manual, Page: 988 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
988 Freescale Semiconductor
Notice that channels 2 and 8 are well within their WCL requirements. The system could be reconfigured
as shown in
Table 24-127 to give channels 0 and 1 a larger margin while still keeping channels 2, 8 and 15
within their WCL requirements.
24.6.6 Endianness
The address of the 24-bit parameters and the most significant byte depends on the endianness of the MCU.
Table 24-128 shows the parameter addresses for big and little endian machines.
24.7 Appendices
24.7.1 Microcycle and I/O timing
24.7.1.1 Execution and channel timing
Figure 24-75 shows the main timings related to microinstruction execution when channels and timebases
run on T2 timing.
Table 24-127. Second-try system with channel 0 and 1 reconfigured
Channel Priority Function
1
,
2
1
0% RAM collision rate
2
CPU clock rate = 40 MHz, or 60 ns per clock period
0 High PWM at 50 kHz (needs a 10-µs WCL)
1 High PWM at 50 kHz (needs a 10-µs WCL)
2 Middle PWM at 5 kHz (needs a 40-µs WCL)
8 Low PPWA at 5 kHz (needs an 80-µs WCL)
15 Low DIO as input at rate of 1 ms
Table 24-128. Parameter addresses and endianness
Parameter
Byte address offset (n = word address offset)
Big endian Little endian
32-bit 4*n
24-bit 4*n + 1 4*n
32-bit parameter’s most significant byte 4*n 4*n + 3
24-bit parameter’s most significant byte 4*n + 1 4*n + 2
Least significant byte 4*n + 3 4*n