NXP Semiconductors MPC5644A, Reference Manual, Page: 879 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 879
associated with output pin actions and Match B recognition for a timed microcode task which has to be
scheduled at a programmed time which may be delayed by the Match A pin action.
Single Match Modes (sm_st, sm_dt, sm_st_e)
There is no difference between plain and enhanced single match modes on an output signal.
In this mode the channel logic is functionally back-compatible to a TPU3 single match output channel.
Match A recognition generates service request and sets the pin state according to OPACA register. It
captures at once the timebase selected by TBSA in CaptureA and the timebase selected by TBSB in
CaptureB.
Match/Transition Pin Action Conflict Resolution
In output signals, matches and/or transitions automatically cause pin actions defined by the OPACA/B
and/or IPACA/B channel control registers (see
Section 24.5.5.1.2, Pin Control Registers ). Simultaneous
matches/transitions may be associated with different, possibly contradictory, pin actions. These conflicts
are resolved according to the
Table 24-56 .
If an OPACA/B = 000 (no action) prevails over non-zero OPAC according to Table 24-56 , then if Match
A/Transition A and Match B/Transition B occur simultaneously, no output pin action occurs, that is: a
match on the action logic with OPAC = 000 inhibits simultaneous actions of the other OPAC, if prevailing
according to
Table 24-56 . That also applies when output actions are caused by inputs (OPAC = 1xx).
24.5.5.4.5 Combining Input and Output Signals
The processing of input signal can be combined with output signal generation. A detected input transition
can trigger an output signal edge, even without microcode intervention, by using OPAC options 1xx.
The channel set-up examples below show these two capabilities combined (see Figure 24-47 ).
The first example implements a fast (no microcode intervention) short-circuit protection feedback
mechanism for driving high-current output devices. The signal after the high-current driver feeds back to
the channel input. The input signal is normally delayed from the output signal by the device turn-on delay.
After the channel output turns on, the channel logic must check if the driver output (connected to the
channel input) follows the driven value after the maximum device turn-on delay. If it does not, the driver
output is probably shorted, and the channel output must be turned off immediately to avoid damaging the
device.
Table 24-56. Simultaneous match pin action priority
Channel mode Priority
em_nb_st / em_nb_dt OPACA
em_b_st / em_b_dt OPACA
bm_st / bm_dt OPACA
m2_st / m2_dt OPACB
m2_o_st / m2_o_dt In these modes there is no possibility of simultaneous matches
user-defined OPACB if M2BM1 = 1 and M1BM2 = 0, OPACA otherwise