NXP Semiconductors MPC5644A, Reference Manual, Page: 1132 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1132 Freescale Semiconductor
When the on-chip ADC abort feature is not enabled, ADC Commands are stored in the CBuffers as they
come and they are executed in the first-in-first-out basis. After the execution of a command in ENTRY1
finishes all commands are shifted one entry. After the shift, ENTRY0 is always empty and ready to receive
a new command. Execution of configuration commands only start when they reach ENTRY1. Consecutive
conversion commands are pipelined and their execution can start while in ENTRY0. This is explained
below.
AD conversion accuracy can be affected by the settling time of the input channel multiplexers. Some time
is required for the channel multiplexers internal capacitances to settle after the channel number is changed.
If the time prior to sampling is not long enough to absorb this settling, then the settling time will take from
ADC sampling time which may result in inaccurate sampling and ultimately compromise conversion result
accuracy - see
Figure 25-82 (a). This could be avoided by switching the multiplexers in preparation for the
next command’s sampling during the AD conversion phase of the current command as showed in
Figure 25-82 (b). In EQADC, this is done in the following way; when a conversion command is in buffer
ENTRY1 and another conversion command is identified in ENTRY0, then the channel number of
ENTRY0 is sent to the
MUX Control Logic some cycles before the sampling phase of the command in
ENTRY0 starts. In this way, sampling for the next command can promptly start after the current
conversion finishes because the internal capacitance of the multiplexers will be settled by that time,
allowing for more accurate sampling. This is specially important for applications that require high
conversion speeds, that is with the ADC running at maximum clock frequency and with the analog input
voltage sampling time set to a minimum (2 ADC clock cycles), when the short sampling time does not
allow the multiplexers to completely settle. The second advantage of pipelining conversion commands is
to provide precise conversion intervals, which means the time intervals between two consecutive
conversions are the same. This is important for any digital signal process application.
When the on-chip ADC abort feature is enabled, ADC Commands from CFIFO0 should be considered
immediately, even stopping the execution of some command that is already in ENTRY1. When the abort
request is sent to the ADC, the already stored commands in the CBuffers are copied in a temporary set of
registers. The first ADC command from CFIFO0 is sent after the abort acknowledge indication from ADC.
The process is the same as usual until the transfer of the last command from CFIFO0. Then the temporarily
stored commands that were postponed by the abortion are recovered and they are pipelined for execution.
After the last command from this temporary memory is transferred, the next commands are pipelined from
the CFIFOs.