NXP Semiconductors MPC5644A, Reference Manual, Page: 596 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
596 Freescale Semiconductor
18.4.4.4 Flash ECC Address Register (ECSM_FEAR)
The ECSM_FEAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in
the platform flash memory. Depending on the state of the ECC Configuration Register, an ECC event in
the flash causes the address, attributes and data associated with the access to be loaded into the
ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDRs, and the appropriate flag (F1BC or
FNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
18.4.4.5 Flash ECC Master Number Register (ECSM_FEMR)
The ECSM_FEMR is a 4-bit register for capturing the XBAR bus master number of the last,
properly-enabled ECC event in the flash memory. Depending on the state of the ECC Configuration
Register, an ECC event in the flash causes the address, attributes and data associated with the access to be
loaded into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and the
appropriate flag (FNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x0050 (0xFFF4_0054)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R FEAR[31:16]
W
Reset — — — — — — — — — — — — — — — —
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FEAR[15:0]
W
Reset — — — — — — — — — — — — — — — —
= Unimplemented
Figure 18-7. Flash ECC Address Register (ECSM_FEAR)
Table 18-9. ECSM_FEAR field description
Name Description
0–31
FEAR[31:0]
Flash ECC Address Register
This 32-bit register contains the faulting access address of the last, properly-enabled flash ECC
event.