NXP Semiconductors MPC5644A, Reference Manual, Page: 1063 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1063
25.5.3.2 ADC Time Stamp Control Register (ADC_TSCR)
The ADC Time Stamp Control Register (ADC_TSCR) contains a system clock divide factor used in the
making of the time base counter clock. It determines at what frequency the time base counter will run.
ADC_TSCR can be accessed by configuration commands sent to CBuffer0 or to CBuffer1. A data write
to ADC_TSCR through a configuration command sent to CBuffer0 will write the same memory location
as when writing to it through a configuration command sent to CBuffer1.
NOTE
Simultaneous write accesses from CBuffer0 and CBuffer1 to ADC_TSCR
are not allowed.
0b11110 62 63
0b11111 64 65
ADC0/1 Register address: 0x02
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0
TBC_CLK_PS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 25-39. ADC Time Stamp Control Register (ADC_TSCR)
Table 25-36. ADC Time Stamp Control Register (ADC_TSCR) field description
Field Description
12-15
TBC_CLK_PS
[0:3]
Time Base Counter Clock Prescaler
The TBC_CLK_PS field contains the system clock divide factor for the time base counter. It
controls the accuracy of the time stamp. The prescaler is disabled when TBC_CLK_PS is
set to 0b0000.
Table 25-37. Clock Divide Factor for Time Stamp
TBC_CLK_PS[0:3]
System Clock Divide
Factor
Clock to Time Stamp
Counter for a 120 MHz
System Clock (MHz)
0b0000 Disabled Disabled
0b0001 1 120
0b0010 2 60
Table 25-35. System Clock Divide Factor for ADC Clock (continued)
ADC0/1_CLK_PS[0:4]
System Clock Divide Factor
ADC0/1_ODD_
PS = 0
ADC0/1_ODD_
PS = 1