NXP Semiconductors MPC5644A, Reference Manual, Page: 807 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 807
30 CIOC—Channel Interrupt Overflow Clear
1: clear status bit.
0: keep status bit unaltered.
These bits are mirrored in ETPU_CIOSR – see Section 24.4.6.3, ETPU_CIOSR – eTPU Channel Interrupt
Overflow Status Register . See also Section 24.5.2.2.2, Interrupt and data transfer request overflow .
2-7 Reserved
8 DTRS—Data Transfer Request Status
1: Channel has a pending data transfer request.
0: Channel has no pending data transfer request.
8 DTRC—Data Transfer Request Clear
1: clear status bit.
0: keep status bit unaltered
These bits are mirrored in ETPU_CISR – see Section 24.4.6.2, ETPU_CDTRSR – eTPU Channel Data
Transfer Request Status Register . See also Section 24.5.9.3.10, Channel interrupt and data transfer
requests .
9 DTROS—Data Transfer Request Overflow Status
1: data transfer request overflow asserted for this channel
data transfer request overflow negated for this channel
9 DTROC—Data Transfer Request Overflow Clear
1: clear status bit.
keep status bit unaltered.
These bits are mirrored in ETPU_CDTROSR – see Section 24.4.6.4, ETPU_CDTROSR – eTPU Channel
Data Transfer Request Overflow Status Register . See also Section 24.5.2.2.2, Interrupt and data transfer
request overflow .
10-15 Reserved
16 IPS—Channel Input Pin State
This bit shows the current value of the filtered channel input signal state
17 OPS—Channel Output Pin State
This bit shows the current value driven in the channel output signal, including the effect of the external
output disable feature (see
Section 24.3.2.4, ipp_ind_etpu_odis_[1|2]([0 – 3]) eTPU Channel Output
Disable Signals . If the channel input and output signals are connected to the same pad, OPS reflects the
value driven to the pad (if OBE = 1). This is not necessarily the actual pad value, which drives the value in
the bit IPS.
Table 24-34. ETPU_CxSCR field description
Field Description