NXP Semiconductors MPC5644A, Reference Manual, Page: 825 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 825
remains asserted. The assertion of Global Exception by one of the sources above does not prevent the
others from asserting it too, so any number of them, in any combination, can be flagged.
NOTE
There can be a race between the clear of a Global Exception and occurrence
of a new set condition, such that the set happens just before the clear and
cannot be sensed by the Host. Therefore, Global Exception cannot be used
as a normal interrupt source: it should only be used for emergency
procedures.
24.5.2.2.2 Interrupt and data transfer request overflow
If a Channel Interrupt was issued, its status bit is still set, and microcode issues another Channel Interrupt,
the Interrupt Overflow status bit is set for that channel. Interrupt Overflow status can be checked by the
Host in Channel Status register ETPU_CxSCR bit CIOS (
Section 24.4.7.2, ETPU_CxSCR – eTPU
Channel x Status Control Register ), mirrored in register ETPU_CIOSR ( Section 24.4.6.3, ETPU_CIOSR
– eTPU Channel Interrupt Overflow Status Register ). Interrupt Overflow status is not cleared
automatically when Interrupt Status is cleared. The same mechanism and respective registers
(ETPU_CDTROSR) are available for Data Transfer Requests.
If interrupt is set and cleared at the same time, set prevails and overflow is not altered (keeps the same state
as it was before, asserted or not).
Global Exception has no overflow status.
24.5.2.3 Parameter access
24.5.2.3.1 Parameter access widths
From the Host side the SPRAM address space is mapped in bytes, and each 32-bit parameter occupies 4
contiguous, aligned bytes. The Host can read/write the SPRAM by 8-, 16-, or 32-bit accesses in aligned
addresses.
In 32-bit access, Host can access all 32 bits or only the lower 24 bits with an automatic sign extension (see
Section 24.5.2.3.4, Parameter sign extension area ).
24.5.2.3.2 Parameter addresses and endianness
To access parameter number xxx , eTPU Microengine(s) would select address xxx. The Host would add
(xxx*4) to the SPRAM base address to access the same parameter. For example, parameter 0x101 is seen
by the Host in (SPRAM base a0x404) . An example of SPRAM memory map is shown in
Figure 24-30 . The Host can access the SPRAM with a 32-bit-wide bus cycle to a four-byte aligned address,
16-bit-wide bus cycle to a two-byte aligned address, or 8-bit wide bus cycle to any byte address.
The address of the 24-bit parameters and the most significant byte depends on the endianness of the MCU.
For more details, see the
Section 24.6.6, Endianness .