NXP Semiconductors MPC5644A, Reference Manual, Page: 1268 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1268 Freescale Semiconductor
24–27
DT[0:3]
Delay after Transfer Scaler
The DT field selects the Delay after Transfer Scaler. This field is only used in master mode. The Delay
after Transfer is the time between the negation of the PCS signal at the end of a frame and the
assertion of PCS at the beginning of the next frame.
Table 30-9 lists the scaler values.
In the Continuous Serial Communications Clock operation the DT value is fixed to one SCK clock
period, The Delay after Transfer is a multiple of the system clock period and it is computed according
to the following equation:
Eqn. 30-3
In the TSB mode the Delay after Transfer is equal to a number formed by concatenation of PDT and
DT fields plus 1 of the SCK clock periods.
See
Section 30.9.5.4, Delay after transfer (tDT) , for more details.
28–31
BR[0:3]
Baud Rate Scaler
The BR field selects the scaler value for the baud rate. This field is only used in master mode. The
prescaled system clock is divided by the Baud Rate Scaler to generate the frequency of the SCK.
Table 30-10 lists the Baud Rate Scaler values.The baud rate is computed according to the following
equation:
Eqn. 30-4
See Section 30.9.5.1, Baud rate generator , for more details.
Table 30-8. DSPI SCK duty cycle
DBR CPHA PBR SCK duty cycle
0 any any 50/50
1 0 00 50/50
1 0 01 33/66
1 0 10 40/60
1 0 11 43/57
1 1 00 50/50
1 1 01 66/33
1 1 10 60/40
1 1 11 57/43
Table 30-9. Delay scaler encoding
Field value Scaler value Field value Scaler value
0000 2 1000 512
0001 4 1001 1024
0010 8 1010 2048
0011 16 1011 4096
Table 30-7. DSPI_CTARn field description in master mode (continued)
Field Descriptions
t
DT
1
f
SYS
-----------
PDT

DT

=
SCK baud rate
f
SYS
PBR
------------
1 DBR +
BR
----------------------

=