NXP Semiconductors MPC5644A, Reference Manual, Page: 1488 / 1735

FlexRay Communication Controller (FlexRay)
MPC5644A Microcontroller Reference Manual, Rev. 6
1488 Freescale Semiconductor
33.5.2.32 System Memory Access Time-Out Register (FR_SYMATOR)
33.5.2.33 Sync Frame Counter Register (FR_SFCNTR)
This register provides the number of synchronization frames that are used for clock synchronization in the
last even and in the last odd numbered communication cycle. This register is updated after the start of the
NIT and before 10 MT after offset correction start.
NOTE
If the application has locked the even synchronization table at the end of the
static segment of an even communication cycle, the CC will not update the
fields SFEVB and SFEVA.
RBIF Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive
message buffers (FR_MBCCSRn[MTD] = 0) the interrupt flag MBIF in the corresponding Message
Buffer Configuration, Control, Status Registers (FR_MBCCSRn) is equal to 1.
0 None of the individual receive message buffers has the MBIF flag asserted.
1 At least one individual receive message buffers has the MBIF flag asserted.
TBIF Transmit Message Buffer Interrupt Flag — This flag is set if for at least one of the individual single
or double transmit message buffers (FR_MBCCSRn[MTD] = 1) the interrupt flag MBIF in the
corresponding
Message Buffer Configuration, Control, Status Registers (FR_MBCCSRn) is equal to 1.
0 None of the individual transmit message buffers has the MBIF flag asserted.
1 At least one individual transmit message buffers has the MBIF flag asserted.
Base + 0x003E Write: Disabled Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
TIMEOUT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Figure 33-32. System Memory Access Time-Out Register (FR_SYMATOR)
Table 33-37. FR_SYMATOR field description
Field Description
TIMEOUT System Memory Access Time-Out — This value defines when a system bus access timeout is
detected. For a detailed description see Section 33.7.1.1, Configure System Memory Access
Time-Out Register (FR_SYMATOR) ” and Section 33.6.19.1.2, System bus access timeout ”.
Base + 0x0040 Additional Reset: RUN Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R SFEVB SFEVA SFODB SFODA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 33-33. Sync Frame Counter Register (FR_SFCNTR)
Table 33-36. FR_CIFR field description (continued)
Field Description