NXP Semiconductors MPC5644A, Reference Manual, Page: 1002 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1002 Freescale Semiconductor
25.1.1.4 AN15/FCK
These pins are configured by setting the Pad Configuration Register 218 (SIU_PCR218) on the SIU.
NOTE
Attempts to convert the input voltage applied to this pin while the FCK
function is selected will result in an undefined conversion result.
As this pin is also used by digital logic, it has reduced analog to digital
conversion accuracy when compared to the AN[0:11,16:39] analog input
pins.
25.1.1.5 External Triggers
The source of the eQADC external triggers can be the eTPU, the eMIOS, or an external signal. The source
is selected by configuring the eQADC Trigger Input Select Register (SIU_ETISR) on the SIU.
25.1.2 Availability of Analog Inputs
Analog inputs ANR, ANS, ANT and ANU are not available on MPC5644A devices.
25.2 Introduction
25.2.1 Module overview
The Enhanced Queued Analog-to-Digital Converter (EQADC) block provides accurate and fast
conversions for a wide range of applications. The EQADC provides a parallel interface to two on-chip
analog-to-digital converters (ADCs), a single master to single slave serial interface to an off-chip external
device, and a parallel side interface to one or more on-chip digital signal processing (DSP) modules (for
example, a decimation filter). The two on-chip ADCs are architected to allow access to all the analog
channels.
The EQADC transfers commands from multiple Command FIFOs (CFIFOs) to the on-chip ADCs or to
the external device. The multiple Result FIFOs (RFIFOs) can receive data from the on-chip ADCs, from
an off-chip external device or from an on-chip DSP module. Data from the on-chip ADCs can be routed
to the side interface, processed by the on-chip DSP and then routed back through the side interface to the
RFIFOs. The EQADC supports software and external hardware triggers from other blocks to initiate
transfers of commands from the CFIFOs to the on-chip ADCs or to the external device. It also monitors
the fullness of CFIFOs and RFIFOs, and accordingly generates DMA or interrupt requests to control data
movement between the FIFOs and the system memory, which is external to the EQADC.