NXP Semiconductors MPC5644A, Reference Manual, Page: 1308 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1308 Freescale Semiconductor
The DSPI master places its second data bit on the SOUT line one system clock after odd numbered SCK
edge if the system frequency to SCK frequency ratio is higher than three. If this ratio is below four the
master changes SOUT at odd numbered SCK edge. The point where the master samples the SIN is selected
by field DSPI_MCR[SMPL_PT].
Table 30-4 lists the number of system clock cycles between the active
edge of SCK and the master Sample point. The master sample point can be delayed by one or two system
clock cycles. Field DSPI_MCR[SMPL_PT] should be set to ‘0’ if the system to SCK frequency ratio is
less than 4.
The following timing diagrams illustrate the DSPI operation with MTFE = 1. Timing delays shown are:
• T
csc
= PCS to SCK assertion delay
• T
acs
= After SCK PCS negation delay
• T
su_ms
= Master SIN setup time
• T
hd_ms
= Master SIN hold time
• T
vd_sl
= Slave data output valid time, time between slave data output SCK driving edge and data
becomes valid.
• T
su_sl
= Data setup time on slave data input
• T
hd_sl
= Data hold time on slave data input
• T
sys
= System clock period
Figure 30-40 shows the modified transfer format for CPHA = 0 and f
sys
/f
sck
= 4. Only the condition where
CPOL = 0 is illustrated. Solid triangles show the data sampling clock edges. The two possible slave
behaviors are shown.
• Signal, marked “SOUT of Ext Slave”, presents regular SPI slave serial output.
• Signal, marked “SOUT of DSPI Slave”, presents DSPI in the slave mode with MTFE bit set.
Other MTFE = 1 diagrams show DSPI SIN input as being driven by a regular external SPI slave,
configured according DSPI master CPHA programming.