NXP Semiconductors MPC5644A, Reference Manual, Page: 1145 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1145
register. t
DT
is the delay between two consecutive serial transmissions, time during which SDS is negated.
When ready to start of the next transmission, the slave must drive the MSB bit of the message on every
positive edge of FCK regardless of the state of the SDS signal. On the next positive edge, the second bit
of the message is conditionally driven according to if an asserted SDS was detected by the slave on the
preceding FCK negative edge. This is an important requisite since the SDS and the FCK are not
synchronous. The SDS signal is not generated by FCK, rather both are generated by the system clock, so
that it is not guaranteed that FCK edges will precede SDS ones. While SDS is negated, the slave
continuously drives its MSB bit on every positive edge of FCK until it detects an asserted SDS on the
immediately next FCK negative edge. See
Figure 25-88 for three situations showing how the slave should
behave according to when SDS is asserted.
NOTE
On the master, the FCK is not used as a clock. Although, the EQADC SSI
behavior is described in terms of the FCK positive and negative edges, all
EQADC SSI related signals (SDI, SDS, SDO, and FCK) are synchronized
by the system clock on the master side. There are no restrictions regarding
the use of the FCK as a clock on the slave device.
25.6.9.1.1 Abort Feature
The master indicates it is aborting the current transfer by negating SDS before the whole data frame has
being shifted out, that is the 26th bit of data being transferred has not being shifted out. The EQADC
ignores the incompletely received message. The EQADC resends the aborted message whenever the
corresponding CFIFO becomes again the highest priority CFIFO with commands bound for not-full
external CBuffer. Refer to
Section 25.6.4.3, CFIFO Common Prioritization and Command Transfer , for
more information on aborts and CFIFO priority.
25.6.9.2 Baud clock generation
As shown in Figure 25-85 , the baud clock generator divides the system clock to produce the baud clock.
The BR field in Section 25.5.2.13, EQADC SSI Control Register (EQADC_SSICR) , selects the system
clock divide factor as in Table 25-24 .
1
1. Maximum FCK frequency is highly dependable on track delays, master pad delays, and slave pad delays.
BaudClockFrequency
SystemClockFrequency MHz
 
SystemClockDivideFactor
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