NXP Semiconductors MPC5644A, Reference Manual, Page: 819 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 819
• Preload of two parameters from the SPRAM into P (32 bits) and DIOB (24 bits).
• Fetch the first instruction of the thread to be executed for the new channel.
• Preset the RAR value (see Section 24.5.8.1.7, RAR – Report Address Register ).
The preload operation is 32-bit wide for P and 24-bit wide for DIOB. The P register is loaded with all the
32-bit parameter. The DIOB register is loaded with the lower 24-bits of the parameter. The microcode can
switch at any time to access the lower 24-bits, upper byte, or all the 32-bits of any parameter in the
SPRAM. Preload of P-DIOB pair of parameters is atomic with respect to Host and CDC accesses, and so
are coherent with their dual-parameter coherent transfers. For more details see
Section 24.5.4, Parameter
sharing and coherency .
No instructions are executed at the engine where the time slot transition period occurs, but the other engine
can execute normally. Match A/B is unconditionally disabled on the second TST microcycle, if
IPACA/B = 0xx (respectively). During the rest of time slot transition, match recognition can be disabled
or not, depending on IPACA/B field and ME. See
Section 24.5.5.2, Match Recognition .
Time Slot Transition takes a minimum of 3 microcycles (6 system clocks), which may be extended due to
SPRAM arbitration wait-states for the first preload access (see
Section 24.5.4.5, SPRAM Arbitration ).
When no wait-states are received ( Figure 24-27 ), DIOB is preloaded twice, one for each PP value, and the
correct value remains in DIOB when the Entry Point is loaded. Figure 24-28 and Figure 24-29 show the
timing for one and two wait-states, respectively.
Registers B, C, D and SR are not altered by TST and keep their values from the previous thread. The values
of registers A, MACL and MACH are not guaranteed at the thread start.