NXP Semiconductors MPC5644A, Reference Manual, Page: 1338 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1338 Freescale Semiconductor
31.1.4 Overview
The eSCI block allows asynchronous serial communications with peripheral devices and other CPUs. It
includes special support to interface to LIN slave devices.
Asserted A signal that is asserted is in its active state. An active low signal changes from logic level one to logic level
zero when asserted, and an active high signal changes from logic level zero to logic level one.
Preamble The term preamble describes an idle character which is transmitted by the eSCI module.
Bit time Duration of a single bit in a transmitted byte field or character, equivalent to the duration of one transmitter
clock cycle defined in
Section 31.4.3.2, Transmitter clock
frame Entity that consists of the start bit followed by payload bits followed by one ore more stop bits
LIN byte field Special instance of a frame
SCI frame Special instance of a frame
LIN frame Sequence of break character followed by LIN byte fields
LIN TX frame A LIN frame with the frame header, data byte fields, and checksum field transmitted by the eSCI module
LIN RX frame A LIN frame with the header field transmitted by the eSCI module and the data byte fields and checksum field
received by the eSCI module
module is idle Module is idle, described in Section 31.1.6.1, Module idle condition
Table 31-2. Glossary (continued)
Term Definition
RECEIVE
SHIFT REGISTER

16
RXD
POLARITY
CONTROL
BAUD RATE
GENERATOR
RECEIVE
DATA REGISTER
TXD
TRANSMIT
DATA REGISTER
TRANSMIT
SHIFT REGISTER
INTERNAL DATA BUS
RECEIVE
CONTROL
WAKE UP
CONTROL
FRAME FORMAT
CONTROL
TRANSMIT
CONTROL
INTERNAL DATA BUS
INTERRUPT
GENERATION
LOOP
CONTROL
CPU
IRQ
RX DMA
CHANNEL
DMA
CTRL
TX DMA
CHANNEL
DMA
CTRL
LIN PE
TCLK
RCLK
BUS
CLK