NXP Semiconductors MPC5644A, Reference Manual, Page: 1274 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1274 Freescale Semiconductor
30.8.2.7 DSPI PUSH TX FIFO Register (DSPI_PUSHR)
The DSPI_PUSHR provides means to write to the TX FIFO. Data written to this register is transferred to
the TX FIFO. See
Section 30.9.2.4, Transmit first-in first-out (TX FIFO) buffering mechanism ” for more
information. Eight or 16-bit write accesses to the DSPI_PUSHR transfers all 32 register bits to the TX
FIFO.
The register structure is different in master and slave modes. In master mode the register provides 16-bit
commands and 16-bit data to the TX FIFO. In slave mode all 32 register bits can be used as data,
supporting up to 32-bit SPI frame operation.
14
RFDFRE
Receive FIFO Drain Request Enable
The RFDFRE bit enables the RFDF flag in the DSPI_SR to generate a request. The RFDFDIRS bit
selects between generating an interrupt request or a DMA request.
0 RFDF interrupt requests or DMA requests are disabled
1 RFDF interrupt requests or DMA requests are enabled
15
RFDFDIRS
Receive FIFO Drain DMA or Interrupt Request Select
The RFDFDIRS bit selects between generating a DMA request or an interrupt request. When the
RFDF flag bit in the DSPI_SR is set, and the RFDFRE bit in the DSPI_RSER is set, the RFDFDIRS
bit selects between generating an interrupt request or a DMA request.
0 Interrupt request will be generated
1 DMA request will be generated
Address: DSP 0x34
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CONT CTAS EOQ CTCNT PE PP PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-12. DSPI PUSH TX FIFO Register (DSPI_PUSHR) in master mode
Table 30-13. DSPI_RSER field description (continued)
Field Description