NXP Semiconductors MPC5644A, Reference Manual, Page: 553 / 1735

System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 553
16.7.1 System configuration
16.7.1.1 Boot configuration
Two BOOTCFG signals are implemented in MPC5644A MCUs.
The BAM program uses the BOOTCFG0 bit to determine where to read the reset configuration word, and
whether to initiate a FlexCAN or eSCI boot. See
Section 4.7.1, Reset configuration half word (RCHW) ,
for details on the RCHW.
Table 21-3 in Section 21.5.2, BAM program operation , defines the boot modes specified by the
BOOTCFG0 and BOOTCFG1 pins. During the assertion of RSTOUT, the BOOTCFG0 and BOOTCFG1
pins are used to update the RSR and the BAM boot mode.
This device has a second serial boot mode to support not only a Freescale serial boot (compatible with
existing MPC5500 devices), but also a new serial boot with CAN and SCI baudrate auto-detection.
For additional details on the BAM program operation see Chapter 21, Boot Assist Module (BAM) .
16.7.1.2 Pad configuration
The Pad Configuration Registers (PCR) in the SIU allow software control of the static electrical
characteristics of external pins. The multiplexed function of a pin, selection of pull up or pull down
devices, the slew rate of I/O signals, open drain mode for output pins, hysteresis on input pins, and the
drive strength for bus signals can be specified through the PCRs.
16.7.2 Reset control
The reset controller logic is located in the SIU. See Chapter 4, Resets for details on reset operation.
16.7.3 External interrupt request input (IRQ)
The fifteen external interrupt request inputs available on this device (IRQ[0:5,7:15]) connect to the SIU
IRQ inputs. The External IRQ Input Select Register (EIISR) specifies the IRQ[0:5,7:15] signals that are
input to the SIU IRQs.
NOTE
IRQ[6] can be only generated by the deserialized output of the DSPI
module—not the external pins.
External interrupt requests are triggered by rising- and/or falling-edge events that are enabled by setting a
bit in:
• IRQ rising-edge event enable register (SIU_IREER)
• IRQ falling-edge event enable register (SIU_IFEER)
If the bit is set in both registers, both rising- and falling-edge events trigger an interrupt request. Each IRQ
has a counter that tracks the number of system clock cycles that occur between the rising- and falling-edge
events. An IRQ counter exists for each IRQ rising- or falling-edge event enable bit.