NXP Semiconductors MPC5644A, Reference Manual, Page: 103 / 1735

Resets
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 103
4.7.2 Reset configuration timing
The timing diagram in Figure 4-4 shows the sampling of the BOOTCFG[0:1], WKPCFG, and PLLREF
pin for a power-on reset. The timing diagram is also valid for internal/external resets assuming that VDD
and VRC33 are within valid operating ranges. The value of the PLLREF pin is latched at the negation of
the RSTOUT pin. The value of the WKPCFG signal is applied at the assertion of the internal reset signal
(assertion of RSTOUT). The values of the WKPCFG and BOOTCFG[0:1] pins are latched four clock
cycles before the negation of the RSTOUT pin and stored in the SIU_RSR.
Figure 4-4. Reset configuration timing
1
327,680 system clocks
2
261,600 system clocks
RSTOUT
RESET
Internal
Reset
VDD
POR
PLL
XTAL Clock Ready
Crystal powering up or acquiring lock
WKPCFG, PLLREF,
User drives
config pins relative
to RSTOUT
PLLREF is
(4 clock cycles)
CNT
1
clock cycles
‘Don’t Care’ and WKPCFG is
treated as ‘1’ during POR assertion.
PLLREF and WKPCFG
are applied, but not latched.
NOTE:
1. The clock count CNT depends on the reset source and type of clock reference. Please refer to
Table 4-3 .
BOOTCFG[0:1]