NXP Semiconductors MPC5644A, Reference Manual, Page: 367 / 1735

Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 367
The peripheral or software configurable interrupt request asserts when the
PRI
n value in the interrupt priority select register (INTC_PSR n ) is greater
than the PRI n value in interrupt current priority register (INTC_CPR).
If an asserted peripheral or software configurable interrupt request negates
before the processor acknowledges its request, the interrupt request can
reassert and remain asserted. If this occurs, the processor uses the
INTC_PSR
n value to locate the IRQ vector, and updates the PRI n value in
the INTC_CPR with the PRI n value in INTC_PSR n .
Clearing the peripheral interrupt request enable bit for the peripheral
initiating the request, or setting the IRQ mask bit has the same consequences
as clearing its flag bit. Setting its enable bit or clearing its mask bit while its
flag bit is asserted has the same effect on the INTC as an interrupt event
setting the flag bit.
0x1D90 473 ESCIC_SR[TDRE]
ESCIC_SR[TC]
ESCIC_SR[RDRF]
ESCIC_SR[IDLE]
ESCIC_SR[OR]
ESCIC_SR[NF]
ESCIC_SR[FE]
ESCIC_SR[PF]
ESCIC_SR[BERR]
ESCIC_SR[RXRDY]
ESCIC_SR[TXRDY]
ESCIC_SR[LWAKE]
ESCIC_SR[STO]
ESCIC_SR[PBERR]
ESCIC_SR[CERR]
ESCIC_SR[CKERR]
ESCIC_SR[FRC]
ESCIC_SR[OVFL]
Combined Interrupt Requests of ESCI Module C:
Transmit Data Register Empty, Transmit
Complete, Receive Data Register Full, Idle line,
Overrun, Noise Flag, Framing Error Flag, and
Parity Error Flag interrupt requests, SCI Status
Register 2 Bit Error interrupt request, LIN Status
Register 1 Receive Data Ready, Transmit Data
Ready, Received LIN Wakeup Signal, Slave
TimeOut, Physical Bus Error, CRC Error,
Checksum Error, Frame Complete interrupts
requests, and LIN Status Register 2 Receive
Register Overflow
0x1DA0 474—
483
Reserved Reserved
0x1E40 484—
485
REACM[4]
REACM[5] Reaction Channel 4
–
5 Interrupts
1
The maximum vector number (485) is used to identify the location of the last available interrupt vector in
memory for this device. Because blocks of memory throughout the total memory map are used for other
purposes, the maximum vector number does not indicate the total number of available interrupt sources
for this device.
2
Interrupt requests from the same module location are ORed together.
Table 15-8. Interrupt Request Sources (continued)
Hardware
Vector
Mode
Offset
Vector
Number
1
Source
2
Description