NXP Semiconductors MPC5644A, Reference Manual, Page: 1267 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1267
10–11
PASC[0:1]
After SCK Delay Prescaler
The PASC field selects the prescaler value for the delay between the last edge of SCK and the
negation of PCS. See the ASC field description how to compute the After SCK delay. In the TSB
mode the PASC field has no effect.
00 After SCK delay prescaler value is 1
01 After SCK delay prescaler value is 3
10 After SCK delay prescaler value is 5
11 After SCK delay prescaler value is 7
12–13
PDT[0:1]
Delay after Transfer Prescaler
The PDT field selects the prescaler value for the delay between the negation of the PCS signal at the
end of a frame and the assertion of PCS at the beginning of the next frame. The PDT field is only
used in master mode. In the TSB mode the PDT field defines two MSB bits of the Delay after Transfer.
See the DT field description for details on how to compute the Delay after Transfer.
00 Delay after Transfer prescaler value is 1
01 Delay after Transfer prescaler value is 3
10 Delay after Transfer prescaler value is 5
11 Delay after Transfer prescaler value is 7
14–15
PBR[0:1]
Baud Rate Prescaler
The PBR field selects the prescaler value for the baud rate. This field is only used in master mode.
The Baud Rate is the frequency of the Serial Communications Clock (SCK). The system clock is
divided by the prescaler value before the baud rate selection takes place. See the BR field description
for details on how to compute the baud rate.
00 Baud Rate prescaler value is 2
01 Baud Rate prescaler value is 3
10 Baud Rate prescaler value is 5
11 Baud Rate prescaler value is 7
16–19
CSSCK[0:3]
PCS to SCK Delay Scaler
The CSSCK field selects the scaler value for the PCS to SCK delay. This field is only used in master
mode. The PCS to SCK delay is the delay between the assertion of PCS and the first edge of the
SCK.
Table 30-9 list the scaler values.The PCS to SCK delay is a multiple of the system clock period
and it is computed according to the following equation:
Eqn. 30-1
See Section 30.9.5.2, PCS to SCK delay (t
CSC
) , for more details.In the TSB mode the field has no
effect.
20–23
ASC[0:3]
After SCK Delay Scaler
The ASC field selects the scaler value for the After SCK Delay. This field is only used in master mode.
The After SCK Delay is the delay between the last edge of SCK and the negation of PCS.
Table 30-9
list the scaler values.The After SCK Delay is a multiple of the system clock period, and it is computed
according to the following equation:
Eqn. 30-2
See Section 30.9.5.3, After SCK delay (t
ASC
) , for more details. In the TSB mode the field has no
effect.
Table 30-7. DSPI_CTARn field description in master mode (continued)
Field Descriptions
t
CSC
1
f
SYS
----------- PCSSCK CSSCK
 
=
t
ASC
1
f
SYS
----------- PASC

ASC

=