NXP Semiconductors MPC5644A, Reference Manual, Page: 1203 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1203
Input buffer overrun is detected and flagged by the DECFILTER_MSR bit IVR. The idle (BSY = 0)
Decimation Filter is able to receive two consecutive input writes without input overrun. For more details,
see
Section 26.5.3.1, Input buffer overrun ”.
When the selected input source is the PSI master block, the PSI master may send timestamp data after
related sample data for filtering. The timestamp is sent back to the PSI following the respective filter
output, using the same request mechanism. As the decimation filter takes several clock cycles to process
a sample, the timestamp is copied into an internal timestamp register until the filtered output is sent out,
therefore freeing the input buffer for yet another sample data.
When the input buffer is loaded with a sample data coming from the PSI interface and enhanced debug
monitor enabled is enabled (DECFILTER_MCR bits ISEL = 0, EDME = 1), input DMA or interrupt
requests are asserted, so that the PSI input samples can be monitored from the device slave-bus interface.
These interrupt or DMA requests result in input read accesses from the DECFILTER_IB register, unlike
write accesses needed when the same requests are made and the device slave-bus interface is selected for
input (ISEL = 1). Only the sample data input (not timestamps), can be monitored in this way. See also
Section 26.5.14, Enhanced debug monitor description ”.
Soft reset clears the input buffer indication flags and any data write/read request that was generated in any
mode.
26.5.3.1 Input buffer overrun
An input overrun occurs when the input buffer is holding input data and new data is received by the filter.
See
Section 26.5.3, Input buffer description , for details of the input buffer.
The input buffer overrun can occur only when the input is enabled (DECFILTER_MCR bit IDIS = 0), and
in the following cases:
• When the input buffer has sample data to be processed but the filter is busy and another input (data
or timestamp) is received.
• When the input buffer has a timestamp, the internal timestamp register is loaded and the next input
data is received.
As an example of the input data sequence, assume that the filter is enabled and not busy, and all registers
are empty. Then a word of sample data is received followed by a timestamp and another word of sample
data. No input overrun occurs in this case, because the first sample is immediately transferred to the tap
input register, the timestamp is immediately transferred to the internal timestamp storage register, and the
second sample can be held in the input buffer until the end of the processing of the sample data by the filter.
The input overrun may occur if more input is received before the end of the processing, or if the filter is
busy at the beginning of the received sequence.
When the filter is in bypass/disable mode (DECFILTER_MCR field FTYPE = 00), the data from the input
buffer is transferred to the output buffer, if it is not already full. If the output buffer is full, the input buffer
is loaded, and another word of input data is sent, then an input overrun occurs.
NOTE
Configuring ISEL = 1, MIXM = 1 and FTYPE = 00 (bypass), writes to the
DECFILTER_IB are routed directly to the PSI output.