NXP Semiconductors MPC5644A, Reference Manual, Page: 95 / 1735

Resets
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 95
The RSTOUT pin can also be asserted by a write to the SER bit of the System Reset Control Register
(SIU_SRCR). Asserting SIU_SRCR[SER], the RSTOUT duration will follow the value specified in
Table 4-3 .
4.4 FMPLL lock gating signal
The FMPLL Loss of Lock reset request is connected to both a reset request and a reset gating signal in the
SIU. The FMPLL asserts the Loss of Lock reset request until the PLL has achieved lock.
4.5 Reset source descriptions
For the following reset source descriptions refer to the reset flow diagrams in Figure 4-1 and Figure 4-2 .
Figure 4-1 shows the reset flow for assertion of the RESET pin. Figure 4-2 shows the internal processing
of reset for all reset sources.
Table 4-3. Timing for reset sources
Reset source Description
Number of clocks
Crystal reference External reference
POR Power On Reset 2400 16000
ER External Reset (RESET pin) 2900 16500
LLR Loss of Lock Reset 3400 17000
WTR Watchdog Timer (core) or Debug Reset 3900 17500
SWTR System Software Watchdog Reset 4900 18500
LCR Loss of Clock Reset 5400 19000
SSR SIU Software External Reset 5900 19500
SER SIU Software System Reset 6400 20000