NXP Semiconductors MPC5644A, Reference Manual, Page: 139 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 139
8.1.3.2 Debug mode
In debug mode, the eDMA does not accept new transfer requests when its debug input signal is asserted.
If the signal is asserted during transfer of a block of data described by a minor loop in the current active
channel’s TCD, the eDMA continues operation until completion of the minor loop.
8.2 External signal description
The eDMA has no external signals.
8.3 Memory map and registers
This section provides a detailed description of all eDMA registers.
8.3.1 Module memory map
The eDMA memory map is shown in Table 8-1 . The address of each register is given as an offset to the
eDMA base address. Registers are listed in address order, identified by complete name and mnemonic, and
list the type of accesses allowed.
Table 8-2 shows a graphical representation of the same memory map. In
register names, an “ x ” is used to indicate A or B, depending on which eDMA’s register you are using. If a
register only exists in one of the eDMAs, the register description will state that.
The eDMA’s programming model is partitioned into two regions: the first region defines a number of
registers providing control functions; however, the second region corresponds to the local transfer control
descriptor memory.
Some registers are implemented as two 32-bit registers, and include H and L suffixes, signaling the high
and low portions of the control function.
Table 8-1. eDMA memory map
Offset from
EDMA_BASE
Register Location Size
EDMA_BASE
(0xFFF4_4000)
EDMA_CR—eDMA control register on page 8-147 32
EDM 0x0004 EDMA_ESR—eDMA error status register on page 8-149 32
EDM 0x0008 EDMA_ERQRH—eDMA enable request high register
(channels 63–32) on page 8-152 32
EDM 0x000C EDMA_ERQRL—eDMA enable request low register
(channels 31–00)
on page 8-152 32
EDM 0x0010 EDMA_EEIRLH—eDMA enable error Interpol register
(channels 63–32) on page 8-154 32
EDM 0x0014 EDMA_EEIRL—eDMA enable error interrupt register
(channels 31–00) on page 8-154 32
EDM 0x0018 EDMA_SERQR—eDMA set enable request register on page 8-155 8
EDM 0x0019 EDMA_CERQR—eDMA clear enable request register on page 8-155 8