Power Management Controller (PMC)
MPC5644A Microcontroller Reference Manual, Rev. 6
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Freescale Semiconductor
20
LVFCC
1.2 V LVI clear
This write-only bit is used to clear the LVI interrupt flag associated with the 1.2 V supply. Writing 1 to
this bit clears the LVFC flag. Writing 0 has no effect. Reading this bit always return 0.
0 No effect
1 Clears the LVFC flag
21:23
Reserved
24
LVFR
Reset-pin-supply (VDDEH6) LVI flag
This read-only bit is the LVI interrupt flag associated with the VDDEH6 supply. It is asserted when the
supply falls below the corresponding LVI threshold, and can be cleared by the CPU by writing 1 to
the LVFCR bit. If the LVIER bit is also asserted, an LVI interrupt is sent to the CPU. If LVRER is also
asserted, a system reset will be generated, which will clear the LVFR flag and negate the interrupt
request.
0 No occurrence
1 LVI occurrence detected on the VDDEH6 supply
25
LVFH
VDDEH1 LVI flag
This read-only bit is the LVI interrupt flag associated with the VDDEH1 supply. It is asserted when the
supply falls below the corresponding LVI threshold, and can be cleared by the CPU by writing 1 to
the LVFCH bit. If the LVIEH bit is also asserted, an LVI interrupt is sent to the CPU. If LVREH is also
asserted, a system reset will be generated, which will clear the LVFH flag and negate the interrupt
request.
0 No occurrence
1 LVI occurrence detected on the VDDEH1 supply
26
LVF50
5 V LVI flag
This read-only bit is the LVI interrupt flag associated with the 5 V supply of the voltage
regulator. It can be cleared by the CPU by writing 1 to the LVFC50 bit. If the LVIE50 bit is also
asserted, an LVI interrupt is sent to the CPU. If LVRE50 is also asserted, a system reset will be
generated, which will clear the LVF50 flag and negate the interrupt request.
0 No occurrence
1 LVI occurrence detected on the 5 V supply of the voltage regulator
27
LVF33
3.3 V LVI flag
This read-only bit is the LVI interrupt flag associated with the 3.3 V supply. It is asserted when the
3.3 V supply falls below the corresponding LVI threshold, and can be cleared by the CPU by writing
1 to the LVFC33 bit. If the LVIE33 bit is also asserted, an LVI interrupt is sent to the CPU. If LVRE33
is also asserted, a system reset will be generated, which will clear the LVF33 flag and negate the
interrupt request.
0 No occurrence
1 LVI occurrence detected on the 3.3 V supply
28
LVFC
1.2 V LVI flag
This read-only bit is the LVI interrupt flag associated with the 1.2 V supply. It is asserted when the
1.2 V supply falls below the corresponding LVI threshold, and can be cleared by the CPU by writing
1 to the LVFCC bit. If the LVIC bit is also asserted, an LVI interrupt is sent to the CPU. If LVREC is
also asserted, a system reset will be generated, which will clear the LVFC flag and negate the
interrupt request.
0 No occurrence
1 LVI occurrence detected on the 1.2 V supply
29:31
Reserved
Table 35-5. SR field descriptions (continued)
Field
Description
Summary of Contents for MPC5644A
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