NXP Semiconductors MPC5644A, Reference Manual, Page: 782 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
782 Freescale Semiconductor
Table 24-13. ETPU_TBCR field description
Field Description
0-2 TCR2CTL[2:0]—TCR2 Clock/Gate Control
These bits are part of the TCR2 clocking system (see Section 24.5.6, Time Bases ). They determine the
clock source for TCR2 before the prescaler. TCR2 can count on any detected edge of the TCRCLK signal
or use it for gating system clock divided by 8. After reset - TCRCLK signal rising edge is selected. TCR2
can also be clocked by an internal peripheral timebase signal or system clock divided by 8. TCR2CTL also
determines the TCRCLK edge selected for angle tooth detection in angle mode. See
Table 24-14 .
Table 24-14. TCR2 clock source
TCR2CTL
AM = 0 AM = 1
TCR2 Clock before prescaler Angle tooth detection
000 Gated DIV8 clock (system clock / 8). In
this case, when the external TCRCLK
signal is low, the DIV8 clock is blocked,
preventing it from incrementing the TCR2
prescaler. When the external TCRCLK
signal is high, TCR2 prescaler is
incremented at the frequency of the
system clock divided by 8. do not use with AM = 1
001 Rise transition on TCRCLK signal
increments the TCR2 prescaler. rise edge
010 Fall transition on TCRCLK signal
increments the TCR2 prescaler. fall edge
011 Rise or Fall transition on TCRCLK signal
increments the TCR2 prescaler. both edges
100 DIV8 clock (system clock / 8) do not use with AM = 1
101 Peripheral Timebase clock source
110 do not use with AM = 0 no edge
1
1
TCRCLK edges are not detected by the EAC logic, but they can still be detected by the
channel 0 logic if AM = 01.
111 TCR2 frozen, except as STAC client do not use with AM = 1