NXP Semiconductors MPC5644A, Reference Manual, Page: 1139 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1139
Figure 25-83 shows the maximum configuration of eight external multiplexer chips connected to the
EQADC. The external multiplexer chip selects one of eight analog inputs and connects it to a single analog
output, which is fed to a specific input of the EQADC. The EQADC provides three multiplexed address
signals, MA0, MA1, and MA2, to select one of eight inputs. These three multiplexed address signals are
connected to all eight external multiplexer chips. The analog output of the eight multiplex chips are each
connected to eight separate EQADC inputs, ANR, ANS, ANT, ANU, ANW, ANX, ANY, and ANZ. The
MA pins correspond to the three least significant bits of the channel number that selects ANR, ANS, ANT,
ANU, ANW, ANX, ANY, and ANZ with MA0 being the most significant bit - See
Table 25-71 .
When the external multiplexed mode is selected for either ADC, the EQADC automatically creates the
MA output signals from CHANNEL_NUMBER field of a Command Message. The EQADC also converts
the proper input channel (ANW, ANX, ANY, and ANZ) by interpreting the CHANNEL_NUMBER field.
As a result, up to 64 externally multiplexed channels appear to the conversion queues as directly connected
signals.
Table 25-71. Encoding of MA Pins
1
1
‘0’ means pin is driven LOW and ‘1’ that pin is driven HIGH.
Channel Number selecting ANW, ANX, ANY, ANZ (decimal)
MA0 MA1 MA2
ANW ANX ANY ANZ
64 72 80 88 0 0 0
65 73 81 89 0 0 1
66 74 82 90 0 1 0
67 75 83 91 0 1 1
68 76 84 92 1 0 0
69 77 85 93 1 0 1
70 78 86 94 1 1 0
71 79 87 95 1 1 1