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Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1316
Freescale Semiconductor
Figure 30-51. TSB Downstream frames
shows the two types of MSC downstream frames: command frame and data frame.
The first transmitted bit, called the selection bit, determines the frame type:
•
The selection bit “0” indicates a data frame
•
The selection bit “1” indicates a command frame
Data frame may contain up to two selection bits to support two external slave devices, (so called dual
receiver configuration) or no selection bits at all.
The command frame can be written by software, through SPI TX FIFO, using one or two FIFO entries
with help of the CONT bit. The data frame consists of up to 32 bits from the DSPI_SDR or DSPI_ASDR
registers and up to two zero selection bits. The number of data bits in the data frame is defined by field
DSPI_DSCICR1[TSBCNT].
The selection bit of the MSC command frames (1) can be implemented by software.
To comply with MSC specification, set DSPI_CTARn[LSBFE] to transmit the least significant bit first.
Regardless of the LSBFE bit setting, the Data Frame Selection Bits, if enabled, are always transmitted first,
before the corresponding data subframes.
30.9.8.1
MSC dual receiver support with PCS switchover
When in TSB mode it is possible to switch the set of PCS signals that are driven during the first part of the
frame to a different set of PCS signals during the second part of the frame. The bit, at which this switchover
occurs, is defined by field FMSZ of the DSPI_CTARn register, which is selected by field
DSPI_DSICR[DSICTAS].
Number of the bits, not including the Data Selection Bit, in the first part of the frame is equal to value of
the FMSZ field plus one. During this part of the frame the PCS signal levels are controlled by
DSPI_DSICR DPCSn bits, after that by DSPI_DSICR1 DPCS1_n bits.
t
DT
Data Frame
Invalid
LSB
Active Phase
0
SCK
PCS
Master SOUT
t
DT
= from 1 to 64 T
SCK
Invalid
Command Frame
t
DT
Command Frame = 4 to 32 bits
LSB
1
Selection Bit
Data Frame = 4 to 32 bits
(CPOL = 0)
Active Phase
Summary of Contents for MPC5644A
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Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
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Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
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