NXP Semiconductors MPC5644A, Reference Manual, Page: 834 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
834 Freescale Semiconductor
are no high priority requests and two middle and two low ones. After the first middle service, time slot
count skips 3 assigned to high (no high requests), and services a low priority channel on time slot 4. It
follows the same scheme until there are no other requests and cycle C is truncated, resetting the time slot
counter to 1.
Cycle D begins with a middle request, jumping to time slot 2. During this service two requests arrive, one
high and one middle. Unlike what happened with priority passing, the next serviced is the high priority
channel, as the time slot increments to 3. The second middle priority channel request in cycle D is finally
serviced next, on time slot 5.
Figure 24-33. Priority Passing Disabling Example
24.5.3.2.3 Secondary scheme – priority among channels on the same level
Because channels can randomly request service, channels having the same priority level will inevitably
request service simultaneously. A secondary scheme prioritizes these requests. The Scheduler services
channels on each of the three priority levels, beginning with the lowest numbered channel on that level.
24.5.3.2.4 Priority scheme example
The overall priority scheme simultaneously incorporates both primary and secondary schemes. Combining
both schemes in the following example conveys their correlation.
1. One high-priority and one low priority channels request service, while the Scheduler is in time slot
one. Having its service request bit asserted, a single high-level channel is granted the time slot,
which has high-level priority (primary scheme) and its service grant bit is asserted. At the end of
the thread, the service grant bit is negated (no more requests of high priority level channels).
SLOT Number 6 7 1 2 4 4 5 7 4 6 4 1
2
M H H M L L H H M L M L H M
High Pend Count
Service High
2 1
0 1 0
2 0
- X New Service Requests Arrive at a Specific Priority Level
2 0
X
2
2 2
1
1
1 0
0 0 1
2
2
1
0
2
2
2
DH DM DH DL DL DH DH DM DM DL DM DL
1
ID
0
DH, DH, DL - Default Service High, Middle or Low
ID - Idle (no service request)
ID Slot Assignment
SLOT ASSIGNMENTS:
Fixed Priority Level
Middle Pend Count
Service Middle
Low Pend Count
Service Low
Cycle A Cycle B Cycle C (truncated) Cycle D
3 5
H M
1
1
1
1
0 1
1
0
0
1
H
DM
DH DM
Reset Slot
Number