NXP Semiconductors MPC5644A, Reference Manual, Page: 586 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
586 Freescale Semiconductor
6. With the processor core clocks enabled, the core handles the pending interrupt request.
18.4.3 Miscellaneous User-Defined Control Register (ECSM_MUDCR)
The ECSM_MUDCR is used to specify the number of additional wait states required for the device
SRAM. Please see the device data sheet for details on the cut-off frequency for the addition of 1 wait state.
Register address: ECSM Base + 0x13 (0xFFF4_0013)
0 1 2 3 4 5 6 7
R ENBWCR 0 0 0 PRILVL[0:3]
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented
Figure 18-2. Miscellaneous Wakeup Control Register (ECSM_MWCR)
Table 18-3. ECSM_MWCR field description
Name Description
0
ENBWCR
Enable WCR
0 = MWCR is disabled
1 = MWCR is enabled
4–7
PRILVL[0:3]
Interrupt Priority Level
The interrupt priority level is a core-specific definition. It specifies the interrupt priority level needed
to exit the low-power mode. Specifically, an unmasked interrupt request of a priority level greater than
the PRILVL value is required to exit the mode.
Certain interrupt controller implementations include logic associated with this priority level that
restricts the data value contained in this field to a [0, maximum - 1] range. See the specific interrupt
controller module for details.