NXP Semiconductors MPC5644A, Reference Manual, Page: 1318 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1318 Freescale Semiconductor
To generate/check parity for each subframe set PE bit in each command/TX FIFO entry, forming this
frame.
If the parity error occurs for received SPI frame, the DSPI_SR[SPEF] bit is set. If DSPI_MCR[PES] bit is
set, the DSPI stops SPI frames transmission. To resume SPI operation clear the DSPI_SR[SPEF] or the
DSPI_MCR[PES] bits.
In slave mode the parity is controlled by the PE and PP bits of the DSPI_CTAR0 register similar to the
master mode parity generation without continuous PCS selection.
30.9.9.2 Parity for DSI frames
Parity generation is controlled by PE and PP bits of the DSPI_DSICR similar to the SPI frames. The parity
is calculated and checked for each DSI frame. (DSPI_DSICR[DCONT] bit has no effect on parity
generation.)
If the parity error occurs for received DSI frame, the DSPI_SR[DPEF] bit is set. To resume DSI operation
clear the DSPI_SR[DPEF] bit.
30.9.10 Interrupts/DMA requests
The DSPI has several conditions that can generate interrupt requests and two conditions that can generate
both interrupt or DMA requests.
Table 30-39 lists these conditions. The ‘x’ in the request type columns
indicates which signals are connected on the MPC5644A.
Each condition has a flag bit in the DSPI Status Register (DSPI_SR) and an Request Enable bit in the DSPI
DMA/Interrupt Request Select and Enable Register (DSPI_RSER). The TX FIFO Fill Flag (TFFF) and
RX FIFO Drain Flag (RFDF) generate interrupt requests or DMA requests depending on the TFFFDIRS
and RFDFDIRS bits in the DSPI_RSER.
Table 30-39. Interrupt and DMA request conditions
Condition Flag
Request type
Interrupt DMA
End of Queue (EOQ) EOQF x
TX FIFO Fill TFFF x x
Transfer Complete TCF x
TX FIFO Underflow TFUF x
RX FIFO Drain RFDF x x
RX FIFO Overflow RFOF x
SPI Parity Error SPEF x
DSI Parity Error DPEF x
DSI Deserialized Data Match DDIF x