NXP Semiconductors MPC5644A, Reference Manual, Page: 1627 / 1735

Periodic Interrupt Timer (PIT)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1627
34.3 Signal description
The PIT module has no external pins.
34.4 Memory map and register description
This section provides a detailed description of all registers accessible in the PIT module.
34.4.1 Memory map
Table 34-1 gives an overview of all PIT registers.
NOTE
Register Address = Base A Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
NOTE
Reserved registers will read as 0, writes will have no effect.
34.4.2 Register descriptions
This section describes in address order all the PIT registers and their individual bits.
Table 34-1. PIT memory map
Address offset Use Access Location
0x000 PIT Module Control Register (PITMCR) R/W on page 34-1628
0x004–0x0EC Reserved R —
0x0F0–0x0FC RTI channel
1
1
See Table 34-2 .
0x100–0x10C Timer Channel 0
1
0x110–0x11C Timer Channel 1
1
0x120–0x12C Timer Channel 2
1
0x130–0x13C Timer Channel 3
1
Table 34-2. Timer channel n / RTI channel registers
Address offset Use Access Location
C 0x00 Timer Load Value Register n (LDVALn) R/W on page 34-1628
C 0x04 Current Timer Value Register n (CVALn) R on page 34-1629
C 0x08 Timer Control Register n (TCTRLn) R/W on page 34-1630
C 0x0C Timer Flag Register n (TFLGn) R/W on page 34-1630