NXP Semiconductors MPC5644A, Reference Manual, Page: 1629 / 1735

Periodic Interrupt Timer (PIT)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1629
34.4.2.3 Current Timer Value Register n (CVALn)
These registers indicate the current timer position. In the case of the RTI, this will show a value which is
several cycles old, since it originates from a potentially different clock domain.
Offset channe 0x00 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TSV31 TSV30 TSV29 TSV28 TSV27 TSV26 TSV25 TSV24 TSV23 TSV22 TSV21 TSV20 TSV19 TSV18 TSV17 TSV16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TSV15 TSV14 TSV13 TSV12 TSV11 TSV10 TSV9 TSV8 TSV7 TSV6 TSV5 TSV4 TSV3 TSV2 TSV1 TSV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 34-3. Timer Load Value Register (LDVAL)
Table 34-4. LDVAL field descriptions
Field Description
TSV n Time Start Value Bits
These bits set the timer start value. The timer will count down until it reaches 0, then it will generate
an interrupt and load this register value again. Writing a new value to this register will not restart the
timer, instead the value will be loaded once the timer expires. To abort the current cycle and start a
timer period with the new value, the timer must be disabled and enabled again (see
Figure 34-8 ).
NOTE: For the RTI, the timer should not be set to a value lower than 32 cycles, otherwise interrupts
may be lost, as it takes several cycles to clear the RTI interrupt. For the other timers, this limit does
not apply, however there will be practical limits, since the processor will require several cycles to
service an interrupt.
Offset channe 0x04 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
TVL31 TVL30 TVL29 TVL28 TVL27 TVL26 TVL25 TVL24 TVL23 TVL22 TVL21 TVL20 TVL19 TVL18 TVL17 TVL16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TVL15 TVL14 TVL13 TVL12 TVL11 TVL10 TVL9 TVL8 TVL7 TVL6 TVL5 TVL4 TVL3 TVL2 TVL1 TVL0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 34-4. Current Timer Value Register (CVAL)