NXP Semiconductors MPC5644A, Reference Manual, Page: 761 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 761
The SCM used area is informed to the eTPU address decoding logic through the plug
etpu_scmsize_plug[4:0]. SCM unused area is decoded and returns a fixed opcode, determined by the
register ETPU_SCMOFFDATAR.
Table 24-3. High level memory map
Offset
Use
0x00 – 0x1F System Configuration Registers
0x20 – 0x2F eTPU 1 Time Base Registers
0x30 – 0x3F RESERVED
1
1
Reserved addresses must not be used. Access to these memory positions complete with 0-wait-states, but may
cause unpredictable behavior.
0x40 – 0x4F RESERVED
1
0x50 – 0x5F RESERVED
1
0x60 – 0x6F eTPU 1 Extra Engine Registers
0x70 – 0x7F RESERVED
1
0x80 – 0xFF RESERVED
1
0x100 – 0x13F RESERVED
0x140 – 0x1FF RESERVED
1
0x200 – 0x2FF eTPU 1/2 Global Channel Registers
0x300 – 0x3FF RESERVED
1
0x400 – 0x7FF eTPU 1 Channel Registers
0x800 – 0xBFF eTPU 2 Channel Registers
0xC00 – 0x7FFF RESERVED
1
0x8000 – 0xBFFF
2
2
Actual sizes of SCM and SPRAM are MCU-dependent.
SPRAM
0xC000 – 0xFFFF
2
SPRAM PSE mirror
3
3
Parameter Sign Extension access area, see Section 24.5.2.3, Parameter access
0x10000 – 0x1FFFF
2
SCM
4
4
SCM access is available only when bit VIS = 1 on register ETPU_MCR, under certain conditions (see
Section 24.4.2.1, ETPU_MCR – eTPU Module Configuration Register ).
Table 24-4. Detailed memory map
Offset Use Location
0x00 ETPU_MCR – eTPU Module Configuration Register on page
24-767
0x04 ETPU_CDCR – eTPU Coherent Dual-Parameter Controller Register on page
24-771
0x08 RESERVED