NXP Semiconductors MPC5644A, Reference Manual, Page: 771 / 1735

Enhanced Time Processing Unit (eTPU2)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 771
24.4.2.2 ETPU_CDCR – eTPU Coherent Dual-Parameter Controller Register
eTPU Shared Parameter RAM (SPRAM) can be accessed by the MCU’s processor core and the eTPU’s
microengine(s) concurrently. In general, there is no guaranteed order by which a group of parameters is
accessed, which may lead to a lack of internal consistency if two or more related parameters are read when
only part of them is updated.
The eTPU provides mechanisms to guarantee parameter coherency, including the use of transfer service
thread mechanism. and a mailbox (or “software semaphore”) mechanism.
A third mechanism, the Coherent Dual-parameter Controller (CDC), is also provided. It is used by the
processor core to coherently transfer pairs of parameters between a parameter buffer located on SPRAM
and locations on SPRAM where parameters are accessed directly by the channels. Coherency is
guaranteed by SPRAM access arbitration. Although limited to two parameters only, it has low latency and
wastes no microengine resources.
This register is used to configure and initiate CDC transfers between the parameter buffer area and the
channel parameter area.
1. The host asserts the STS bit to start the data transfer.
2. CDC contends for the SPRAM and starts the transfer.
3. When the data transfer is complete, STS returns to 0. The host receives wait-states for writing
STS = 1 while CDC contends for SPRAM and during the transfer.
4. The write access ends when CDC finishes the transfer. The host receives wait-states during the
CDC transfer.
NOTE
If the host writes to the ETPU_CDCR with STS = 0 or does not write the
STS bit, the CDC transfer does not occur.
CDC programming can be summarized as follows:
1. If it is a write transfer, i.e., from host to channel, write the two parameters into temporary area.
2. Write the ETPU_CDCR with STS = 1 and the remaining CDC programming parameters:
parameter width (32 or 24 bits, field PWIDTH), transfer direction (read or write, field WR),
temporary parameter area base address (field PBBASE), and the absolute addresses of the
parameters to be transferred (concatenation of the fields CTBASE and PARAM0/1).
3. If it is a read transfer, i.e., from channel to host, read the two parameters from the temporary area
into host memory/registers.