External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
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14.5.1.14 Misaligned access support
The EBI has limited misaligned access support. Misaligned non-burst chip-select transfers from internal
masters are supported. The EBI aligns the accesses when it sends them out to the external bus (splitting
them into multiple aligned accesses if necessary), so that external devices are not required to support
misaligned accesses. Burst accesses (internal master) must match the internal bus size (64-bit aligned). See
Section 14.5.2.11, Misaligned access support
” for more details.
14.5.1.15 Compatible with MPC5xx External Bus (with some limitations)
The EBI is compatible with the external bus of the MPC5xx parts, meaning that it supports most devices
supported by the MPC5xx family of parts. However, there are some differences between this EBI and that
of the MPC5xx parts that the user needs to be aware of before assuming that an MPC5xx-compatible
device works with this EBI. See
Section 14.6.6, Summary of Differences from MPC5xx,
for details.
NOTE
Due to testing and complexity concerns, multi-master (or master/slave)
operation between an eSys MCU and MPC5xx is not guaranteed.
14.5.2
External bus operations
The following sections provide a functional description of the external bus, the bus cycles provided for
data transfer operations, and error conditions.
14.5.2.1
External clocking
The CLKOUT signal sets the frequency of operation for the bus interface directly. Internally, the MCU
uses a phase-locked loop (PLL) circuit to generate a master clock for all of the MCU circuitry (including
the EBI) which is phase-locked to the CLKOUT signal. In general, all signals for the EBI are specified
with respect to the rising-edge of the CLKOUT signal, and they are guaranteed to be sampled as inputs or
changed as outputs with respect to that edge.
14.5.2.2
Reset
Upon detection of internal reset assertion, the EBI immediately ends all transactions (abruptly, not through
normal termination protocol), and ignores any transaction requests that take place while reset is asserted.
14.5.2.3
Basic transfer protocol
The basic transfer protocol defines the sequence of actions that must occur on the external bus to perform
a complete bus transaction. A simplified scheme of the basic transfer protocol is shown in
.
Figure 14-8. Basic Transfer Protocol
ARBITRATION ADDRESS TRANSFER DATA TRANSFER
TERMINATION
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