NXP Semiconductors MPC5644A, Reference Manual, Page: 338 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
338 Freescale Semiconductor
BR). This section describes how to configure dual-MCU systems for each of those scenarios, as well as
describing limitations to EBI operation when other pins are missing (TA, TEA, BDIP). More than one
section may apply if the applicable pins are not present on one or both MCUs.
14.6.5.1 Connecting 16-bit MCU to 32-bit MCU (Master/Master or Master/Slave)
This scenario is straightforward. Simply connect DATA[0:15] between both MCUs, and configure both for
16-bit Data Bus Mode operation (DBM=1 in EBI_MCR). Note that 32-bit external memories are not
supported in this scenario.
14.6.5.2 Transfer size with no TSIZ pins (Master/Master or Master/Slave)
Since there are no TSIZ pins to communicate transfer size from master MCU to slave MCU, the internal
SIZE field of the EBI_MCR must be used on the slave MCU (by setting SIZEN=1 in slave’s EBI_MCR).
Anytime the master MCU needs to read or write the slave MCU with a different transfer size than the
current value of the slave’s SIZE field, the master MCU must first write the slave’s SIZE field with the
correct size for the subsequent transaction.
14.6.5.3 No Transfer Acknowledge (TA) Pin
If an MCU has no TA pin available, this restricts the MCU to chip-select accesses only (no MCU->MCU
transfers are possible). Non-chip-select accesses have no way for the EBI to know which cycle to latch the
data. The EBI has no built-in protection to prevent non-chip-select accesses in this scenario; it is up to the
user to make certain they set up chip-selects and external memories correctly to ensure all external
accesses fall in a valid chip-select region.
14.6.5.4 No Transfer Error (TEA) Pin
If an MCU has no TEA pin available, this eliminates the feature of terminating an access with TEA. This
means if an access times out in the EBI bus monitor, the EBI (master) will still terminate the access early,
but there will be no external visibility of this termination, so the slave device might end up driving data
much later, when a subsequent access is already underway. Therefore, the EBI bus monitor should be
disabled when no TEA pin exists.
14.6.5.5 No Burst Data in Progress (BDIP) Pin
If an MCU has no BDIP pin available, this eliminates burst support only if the burstable memory being
used requires BDIP to burst. Many external memories use a self-timed configurable burst mechanism that
does not require a dynamic burst indicator. Check the applicable external memory specification to see if
BDIP is required in your system.
14.6.6 Summary of Differences from MPC5xx
Below is a summary list of the significant differences between this EBI and that of the MPC5xx parts.
• No memory controller support for external masters
— must configure each master in multi-master system to drive its own chip selects