NXP Semiconductors MPC5644A, Reference Manual, Page: 663 / 1735

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 663
22.5.1.1 Channel modes of operation
The mode of operation of channel n is determined by the mode select bits MODE[0:6] in the
EMIOS_CCR[n] (see Table 22-9 for details).
When entering an output mode (except for GPIO mode), the output flip-flop is set to disabled state
according to ODIS bit in the EMIOS_CCR[n].
As the internal counter EMIOS_CCNTR[n] continues to run in all modes (except for GPIO mode), it is
possible to use it as a time base if the resource is not used in the current mode.
To provide smooth waveform generation while allowing A and B registers to be asynchronously updated
during UC operation, the double-buffered modes (MCB, OPWFMB and OPWMB) are provided. In these
modes A and B registers are double buffered.
22.5.1.1.1 General purpose input/output mode (GPIO) mode
In GPIO mode, all input capture and output compare functions are disabled, the internal counter
(EMIOS_CCNTR[n]) is cleared and disabled. All control bits remain accessible. In order to prepare the
channel for a new operation mode, writing to registers EMIOS_CADR[n] or EMIOS_CBDR[n] stores the
same value in registers A1/A2 or B1/B2, respectively. Writing to register EMIOS_ALTA[n] stores a value
only in register A2.
The EMIOS_CCR[n]’s MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1)
modes.
NOTE
It is required that when changing MODE[0:6], the application software goes
to GPIO mode first in order to reset the channel’s internal functions
properly. Failure to do this could lead to invalid and unexpected output
compare or input capture results or the FLAGs being set incorrectly.
In GPIO input mode (MODE[0:6] = 0000000), FLAG generation is determined according to the
EMIOS_CCR[n]’s EDPOL and EDSEL bits and the input pin status can be determined by reading the
EMIOS_CSR[n]’s UCIN bit.
In GPIO output mode (MODE[0:6] = 0000001), the channel is used as a single output port pin and the
value of the EMIOS_CCR[n]’s EDPOL bit is permanently transferred to the output flip-flop.
When changing the EMIOS_CCR[n]’s MODE bits, the application software must go to GPIO mode first
to reset the channel’s internal functions properly. Failure to do this could lead to invalid and unexpected
output compare or input capture results or the FLAGs being set incorrectly.
22.5.1.1.2 Single action input capture (SAIC) mode
In SAIC mode (MODE[0:6] = 0000010), when a triggering event occurs on the input pin, the value on the
selected time base is captured into register A2. The FLAG bit is set along with the capture event to indicate
that an input capture has occurred. EMIOS_CADR[n] returns the value of register A2. As soon as the
SAIC mode is entered exiting from GPIO mode the channel is ready to capture events. The events are
captured as soon as they occur thus reading register A always returns the value of the latest captured event.