NXP Semiconductors MPC5644A, Reference Manual, Page: 294 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
294 Freescale Semiconductor
24-27
SCY
SCY — Cycle length in clocks
This field represents the number of wait states (external cycles) inserted after the address phase in
the single transfer case, or in the first beat of a burst, when the memory controller handles the
external memory access. Values range from 0 to 15. This is the main parameter for determining the
length of the cycle. These bits are ignored when SETA=1.
The total cycle length for the first beat (including the TS cycle) = (2+SCY) external clock cycles.
See
Section 14.6.3.1, Example wait state calculation for related application information.
29-30
BSCY
BSCY — Burst beats length in clocks
1
This field determines the number of wait states (external cycles) inserted in all burst beats except
the first, when the memory controller starts handling the external memory access and thus is using
SCY[0:3] to determine the length of the first beat. These bits are ignored when SETA=1.
The total memory access length for each beat is (1 + BSCY) external clock cycles.
The total cycle length (including the TS cycle) = (2+SCY) + (#beats
2
-1) * (BSCY+1).
1
CAL_BR0-3 registers do not support burst operation.
2
#beats is the number of beats (4,8,16) determined by BL and PS bits in Base Register.
Table 14-9. EBI Option Registers (EBI_OR0-EBI_OR3, EBI_CAL_OR0-3) Field Descriptions
Name Description
Value Meaning
00 0-clock cycle wait states (1 clock per data beat)
01 1-clock cycle wait states (2 clocks per data beat)
10 2-clock cycle wait states (3 clocks per data beat)
11 3-clock cycle wait states (4 clocks per data beat)