NXP Semiconductors MPC5644A, Reference Manual, Page: 289 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 289
14.4.1.3 EBI Bus Monitor Control Register (EBI_BMCR)
The EBI Bus Monitor Control Register controls the timeout period of the bus monitor and whether it is
enabled or disabled.
Figure 14-4. EBI Bus Monitor Control Register (EBI_BMCR)
E0xC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R BMT BME 0 0 0 0 0 0 0
W
RESET: 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 14-7. EBI Bus Monitor Control Register (EBI_BMCR) Field Descriptions
Name Description
16-23
BMT
BMT —Bus Monitor Timing
This field defines the timeout period, in 8 external bus clock resolution, for the Bus Monitor. See
Section 14.5.1.5, Bus Monitor for more details on bus monitor operation.
Timeout Period = (2 + (8 * BMT)) / external bus clock frequency.
24
BME
BME —Bus Monitor Enable
This bit controls whether the bus monitor is enabled for internal to external bus cycles. The BME bit
is ignored (treated as 0) for chip-select accesses with internal TA (SETA=0).
1: Enable bus monitor (for external TA accesses only)
0: Disable bus monitor