NXP Semiconductors MPC5644A, Reference Manual, Page: 1255 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1255
Figure 30-3. DSPI connections for SPI and DSI transfers
Specifically in the TSB configuration, detailed in Section 30.9.8, Timed serial bus (TSB) ”, the DSPI
serializes from 4 to 32 Parallel Input signals or register bits. The TSB downstream frame used to
communicate with a single slave is shown in
Figure 30-38 .
30.4.3 CSI configuration
The CSI configuration allows serialized data to be interleaved with configuration or diagnostic data and
be transferred to a slave device using only one serial link. The CSI configuration supports SPI and DSI
functionality on a frame by frame basis. CSI configuration allows interleaving of DSI data frames from
the eTPU’s and eMIOS’ output channels with SPI commands and data from the TX FIFO. In the CSI
configuration, transmission of SPI data has higher priority than DSI data. The data returned from the bus
slave is either used to drive the eTPUs or eMIOS input channels, or the data is stored in the RX FIFO. The
DSPI only supports CSI configuration in Master Mode.
Figure 30-4 shows an example of how a DSPI can
be used with a deserializing peripheral that supports SPI control for control and diagnostic frames.
Figure 30-4. DSPI Connections for CSI Transfer
30.5 DSPI frequency support
The DSPI supports frequencies up to 40 MHz when used with LVDS outputs (DSPI_B and DSPI_C only),
and frequencies up to 20 MHz in non-LVDS mode.
Table 30-1 shows possible divider settings to achieve
maximum frequency for different system clock frequencies.
Shift Register
SIN
SIN
SOUT
SOUT
SCK
SCK
SS
PCSx
DSPI Master SPI/DSI Slave
Shift Register
Baud Rate
Generator
Shift Register
Shift Register
SIN
SIN
SOUT
SOUT
SCK
SCK
SS0
PCSx
DSPI Master External Slave Deserializer
SS1
PCSy
SPI
DSI
TX Priority
Control
SPI
Frame
Select
Logic
Frame
DSI
Frame
TX FIFO