NXP Semiconductors MPC5644A, Reference Manual, Page: 601 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 601
NOTE
Table 18-15 associates the 8 bits of the ECC syndrome with the exact data
bit in error for single-bit correctable code words. This table follows the bit
vectoring notation where the LSB = 0. The syndrome value of 0x00 implies
no error condition but this value is not readable when the ECSM_PRESR is
read for the no error case.
Table 18-14. ECSM_PRESR field description
Name Description
0–7
PRESR[7:0]
RAM ECC Syndrome Register
This 8-bit syndrome field includes optimized syndrome encoding for the entire 39-bit (32-bit data +
7-bit ECC) code word of each bank for single-bit errors.
Syndrome values for non-correctable errors are not defined.
For correctable single-bit errors, the mapping shown in Table 18-15 associates the 8 bits of the
syndrome with the data bit in error.
Table 18-15. RAM syndrome mapping for single-bit correctable errors
PRESR[7:0] Data bit in error
0x01 ECC ODD[0]
0x02 ECC ODD[1]
0x04 ECC ODD[2]
0x07 DATA ODD BANK[31]
0x08 ECC ODD[3]
0x10 ECC ODD[4]
0x20 ECC ODD[5]
0x40 ECC ODD[6]
0x43 DATA ODD BANK[0]
0x45 DATA ODD BANK[1]
0x46 DATA ODD BANK[2]
0x49 DATA ODD BANK[3]
0x4A DATA ODD BANK[4]
0x4C DATA ODD BANK[5]
0x4F DATA ODD BANK[21]
0x51 DATA ODD BANK[6]
0x52 DATA ODD BANK[7]
0x54 DATA ODD BANK[8]
0x57 DATA ODD BANK[22]
0x58 DATA ODD BANK[9]