NXP Semiconductors MPC5644A, Reference Manual, Page: 603 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 603
18.4.4.10 RAM ECC Master Number Register (ECSM_REMR)
The ECSM_REMR is a 4-bit register for capturing the XBAR bus master number of the last,
properly-enabled ECC event in the RAM memory. Depending on the state of the ECC Configuration
Register, an ECC event in the RAM causes the address, attributes and data associated with the access to
be loaded into the ECSM_REAR, ECSM_PRESR, ECSM_REMR, ECSM_REAT and ECSM_REDR
registers, and the appropriate flag (RNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
0xCF DATA EVEN BANK[21]
0xD1 DATA EVEN BANK[6]
0xD2 DATA EVEN BANK[7]
0xD4 DATA EVEN BANK[8]
0xD7 DATA EVEN BANK[22]
0xD8 DATA EVEN BANK[9]
0xDB DATA EVEN BANK[23]
0xDD DATA EVEN BANK[24]
0xDE DATA EVEN BANK[25]
0xE1 DATA EVEN BANK[10]
0xE2 DATA EVEN BANK[11]
0xE4 DATA EVEN BANK[12]
0xE7 DATA EVEN BANK[26]
0xE8 DATA EVEN BANK[13]
0xEB DATA EVEN BANK[27]
0xED DATA EVEN BANK[28]
0xEE DATA EVEN BANK[29]
0xF0 DATA EVEN BANK[14]
0xF3 DATA EVEN BANK[15]
0xF5 DATA EVEN BANK[16]
0xF6 DATA EVEN BANK[17]
0xF9 DATA EVEN BANK[18]
0xFA DATA EVEN BANK[19]
0xFC DATA EVEN BANK[20]
0xFF DATA EVEN BANK[30]
Table 18-15. RAM syndrome mapping for single-bit correctable errors (continued)
PRESR[7:0] Data bit in error