NXP Semiconductors MPC5644A, Reference Manual, Page: 597 / 1735

Error Correction Status Module (ECSM)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 597
18.4.4.6 Flash ECC Attributes (ECSM_FEAT) Register
The ECSM_FEAT register is an 8-bit register for capturing the XBAR bus master attributes of the last,
properly-enabled ECC event in the flash memory. Depending on the state of the ECC Configuration
Register, an ECC event in the flash causes the address, attributes and data associated with the access to be
loaded into the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and the
appropriate flag (FNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored.
Register address: ECSM Base + 0x0056 (0xFFF4_0056)
0 1 2 3 4 5 6 7
R 0 0 0 0 FEMR[3:0]
W
Reset 0 0 0 0 — — — —
= Unimplemented
Figure 18-8. Flash ECC Master Number Register (ECSM_FEMR)
Table 18-10. ECSM_FEMR field description
Name Description
4–7
FEMR[3:0]
Flash ECC Master Number Register
This 4-bit register contains the XBAR bus master number of the faulting access of the last,
properly-enabled flash ECC event.
Register address: ECSM Base + 0x0057 (0xFFF4_0057)
0 1 2 3 4 5 6 7
R WRITE SIZE[2:0] PROT0 PROT1 PROT2 PROT3
W
Reset — — — — — — — —
= Unimplemented
Figure 18-9. Flash ECC Attributes (ECSM_FEAT) Register